UPD784938 Datasheet, PDF (540/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.3.3 In-service priority register (ISPR)
ISPR shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being
serviced. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request
is set (to 1), and remains set until the service program ends. When a non-maskable interrupt is acknowledged, the bit
corresponding to the priority of that non-maskable interrupt is set (to 1), and remains set until the service program ends.
When an RETI instruction or RETCS instruction is executed, the bit, among those set (to 1) in the ISPR, that corresponds
to the highest-priority interrupt request is automatically cleared (to 0) by hardware.
The contents of ISPR are not changed by execution of an RETB or RETCSB instruction.
RESET input clears ISPR to 00H.
Figure 23-3. In-Service Priority Register (ISPR) Format
7
6
5
ISPR NMIS WDTS 0
4
3
2
1
0 Address After reset R/W
0 ISPR3 ISPR2 ISPR1 ISPR0 0FFA8H
00H
R
(n = 0 to 3)
ISPRn
Priority Level
0 ^{Priority n interrupt not being acknowledged}
1 ^{Priority n interrupt being acknowledged}
WDTS Watchdog Timer Interrupt Service State
0 Watchdog timer interrupt not being
acknowledged
1 _{Watchdog timer interrupt being}
acknowledged
NMIS
NMI Service State
0 ^{NMI interrupt not being acknowledged}
1 ^{NMI interrupt being acknowledged}
Caution In-service priority register (ISPR) is a read-only register. There is a risk of misoperation if a write is
performed on this register.
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Preliminary User’s Manual U13987EJ1V0UM00