UPD784938 Datasheet, PDF (453/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
(2) Serial clock generation in 3-wire serial I/O mode
Selected when the CSCK1 bit of the clocked serial interface mode register (CSIM1) is set (to 1) and SCK1 is output.
(a) Normal mode
The internal clock (fXX) is scaled by the frequency divider, this signal (fPRS) is scaled by the 5-bit counter, and the
signal further divided by 2 is used as the serial clock. The serial clock is given by the following expression:
(Serial clock) =
fXX
(k + 16) • 2ⁿ⁺²
fXX: Oscillator frequency or external clock input frequency
k: Value set in bits MDL3 to MDL0 of BRGC (k = 0 to 14)
n: Value set in bits TPS3 to TPS0 of BRGC (n = 0 to 11)
(b) High-speed mode
When this function is used, bits MDL3 to MDL0 of the baud rate generator control register (BRGC) are all set (1)
(k= 15).
The internal clock (fXX) is scaled by the frequency divider, and this signal (fPRS) divided by 2 is used as the serial
clock. The serial clock is given by the following expression:
(Serial clock) = ^fXX
2ⁿ⁺²
fXX: Oscillator frequency or external clock input frequency
n: Value set in bits TPS3 to TPS0 of BRGC (n = 1 to 11)
Preliminary User’s Manual U13987EJ1V0UM00
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