UPD784938 Datasheet, PDF (554/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.7.3 Maskable interrupt priority levels
The µPD784938 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another
interrupt. Multiple interrupts can be controlled by priority levels.
There are two kinds of priority control, control by default priority and programmable priority control in accordance with
the setting of the priority specification flag. In priority control by means of default priority, interrupt service is performed
in accordance with the priority preassigned to each interrupt request (default priority) (see Table 23-2). In programmable
priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. Interrupt
requests for which multiple interruption is permitted are shown in Table 23-5.
Since the IE flag is cleared (to 0) automatically when an interrupt is acknowledged, when multiple interruption is used,
the IE flag should be set (to 1) to enable interrupts by executing an EI instruction in the interrupt service program, etc.
Table 23-5. Multiple Interrupt Servicing
Priority of Interrupt Currently
Being Acknowledged
No interrupt being
acknowledged
3
ISPR Value
00000000
00001000
2
0000×100
1
0000××10
0
Non-maskable interrupts
0000×××1
1000××××
0100××××
1100××××
IE Flag in PSW
0
1
0
1
1
0
1
0
1
×
×
PRSL Flag in
IMC
×
×
×
0
1
×
×
×
×
×
×
Acknowledgeable Maskable Interrupts
• All macro service only
• All maskable interrupts
• All macro service only
• All maskable interrupts
• All macro service
• Maskable interrupts specified as
priority 0/1/2
• All macro service only
• All macro service
• Maskable interrupts specified as
priority 0/1
• All macro service only
• All macro service
• Maskable interrupts specified as
priority 0
• All macro service only
• All macro service only
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Preliminary User’s Manual U13987EJ1V0UM00