UPD784938 Datasheet, PDF (500/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
20.5 Interrupt Operations of IEBus Controller
20.5.1 Interrupt control block
<Interrupt request signal>
1. Communication error
2. Start interrupt
3. Status communication
4. End of communication
5. End of frame
6. Transmit data write request
7. Receive data read request
(IEERR)
(START)
(STATUS)
(ENDTRANS)
(ENDFRAM)
(STATTX)
(STATRX)
1 through 5 of the above interrupt requests 1 are assigned to the interrupt status register (ISR). For details, refer to
Table 20-9 Interrupt Requests.
The configuration of the interrupt control block is illustrated below.
Figure 20-28. Configuration of Interrupt Control Block
IEERR
START
STATUS
ENDTRANS
ENDFRAM
STATTX
STATRX
INTIE1
INTIE2
IEBus macro
Interrupt control block
78K/IV CPU
Cautions 1. With regard to ORed output of STATTX, STATRX, faster processing is aimed for by using a macro
service.
2. With regard to ORed output of IEERR, START, STATUS, ENDTRANS, ENDFRAM, check the
interrupt generation source using vector interrupt processing.
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Preliminary User’s Manual U13987EJ1V0UM00