UPD784938 Datasheet, PDF (385/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 12 TIMER 3
12.7 Cautions
(1) There is a possibility of malfunction if the next register contents are rewritten while the timer 3 is operating (when the
CE3 bit of the timer control register 0 (TMC0) is set). The malfunction occurs as there is no defined order of priority
in the event of contention between the timings at which the hardware function changes due to a register rewrite and
the status changes in the function prior to the rewrite.
When the contents of the following register are rewritten, counter operations must be stopped first to ensure stability.
• Prescaler mode register 0 (PRM0)
(2) If the compare register (CR30) and timer counter 3 (TM3) contents match when an instruction that stops TM3 operation
is executed, the TM3 count operation stops, but an interrupt request is generated.
If you do not want an interrupt to be generated when TM3 operation is stopped, interrupts should be masked by means
of interrupt the mask register before stopping the TM3.
Example
Program in which an interrupt request may be
generated
CLR1 CE3
← Interrupt request generated
SET1 CMK30 ^{by timer 3 here}
Program in which an interrupt request is not generated
SET1 CMK30 ← Disables interrupts from timer 3
CLR1 CE3
CLR1 CIF30 ← Clears timer 3 interrupt request flag
(3) There is a delay of up to one count clock between the operation that starts a timer 3 (CE3 ← 1) and the actual start
of the timer 3 (see Figure 12-12).
For example, if a timer 3 is used as an interval timer, the first interval will be extended by up to one clock. The second
and subsequent intervals will be as specified.
Figure 12-12. Operation when Counting is Started
Count clock
TM3
0
0
1
2
3
CE3
Timing at which count actually starts
Software count start command (CE3 ← 1)
Preliminary User’s Manual U13987EJ1V0UM00
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