UPD784938 Datasheet, PDF (204/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 7 REAL-TIME OUTPUT FUNCTION
7.3 Real-time Output Port Accesses
The port 0 buffer registers (P0H, P0L) are mapped onto mutually independent addresses in the SFR area as shown in Figure
7-3.
When the 4-bit × 2-channel real-time output function is specified, data can be set in the P0H, P0L independently of each other.
When the 8-bit × 1-channel real-time output function is specified, data can be set in P0H and P0L by writing 8-bit data to either
one of the P0H or P0L.
Table 7-1 shows the operations when port 0, the P0H and P0L are manipulated.
Figure 7-3. Port 0 Buffer Register (P0H, P0L) Configuration
High-order 4 bits Low-order 4 bits
0FF0EH
P0L
0FF0FH
P0H
Table 7-1. Operations when Port 0 and Port 0 Buffer Registers (P0H, P0L) are Manipulated
Operation Mode
Register
8-bit port mode
P0
P0L
P0H
8-bit real-time output
P0
port mode
P0L
P0H
4-bit separate real-time P0
output port mode
P0L
P0H
P00 to P03: Ports
P0
P04 to P07: Real-time
P0L
output port mode
P0H
P00 to P03: Real-time
P0
output port mode
P0L
P04 to P07: Ports
P0H
Read Operation
High-Order 4 Bits
Low-Order 4 Bits
Output latch
Buffer register^Note
Buffer register^Note
Output latch
Buffer register
Buffer register
Output latch
Buffer register^Note
Buffer register^Note
Output latch
Buffer register^Note
Buffer register^Note
Output latch
Buffer register^Note
Buffer register^Note
Write Operation
High-Order 4 Bits
Low-Order 4 Bits
Output latch
—
Buffer register
Buffer register
—
—
Buffer register
Buffer register
—
—
Buffer register
Buffer register
—
—
Output latch
—
Buffer register
Buffer register
—
Output latch
—
—
Buffer register
Buffer register
—
Note The contents of P0H are read from the high-order 4 bits, and the contents of P0L from the low-order 4 bits.
Remark — : The output latch and port 0 buffer registers are not affected.
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Preliminary User’s Manual U13987EJ1V0UM00