UPD784938 Datasheet, PDF (630/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
(2) Refresh area specification register (RFA)
RFA is an 8-bit register that specifies the areas on which refresh operations can be performed at the same time as
memory access operations.
RFA can be read or written to with an 8-bit manipulation instruction and bit manipulation instruction. The RFA format
is shown in Figure 24-16.
RESET input clears RFA to 00H.
Figure 24-16. Refresh Area Specification Register (RFA) Format
7
6
5
4
3
2
1
0
Address After reset R/W
RFA RFA7 RFA6
RFA5
RFA4
RFA3 RFA2
RFA1
RFA0 0FFCDH 00H R/W
(n = 0 to 7)
RFAn
Refresh
Specification
080000H to
040000H to
020000H to
010000H to
00C000H to
008000H to
004000H to
000000H to
Area
0FFFFFH 07FFFFH 03FFFFH 01FFFFH 00FFFFH 00BFFFH 007FFFH 003FFFH
0
Refreshing performed at same time as memory access operations in corresponding block
1
Refreshing performed exclusively from memory access operations in corresponding block
24.3.2 Operations
(1) Pulse refresh operation
To support the pulse refresh cycles of pseudo-static RAM, refresh pulses are output from the REFRQ pin in
synchronization with bus cycles.
The system clock frequency and bits 1 and 0 (RFT1/RFT0) of the refresh mode register (RFM) are adjusted so that
512 or more refresh pulses are generated in an 8 ms period.
Table 24-1. System Clock Frequency and Refresh Pulse Output Cycle when Pseudo-Static RAM is Used
System Clock Frequency
(fCLK) MHz
8.192 < fCLK ≤ 16
4.096 < fCLK ≤ 8.192
2.048 < fCLK ≤ 4.096
Refresh Pulse Output Cycle Specification
128/fCLK
64/fCLK
32/fCLK
RFT1
1
0
0
RFT0
0
1
0
These pulse refresh operations are performed so that they do not overlap external memory access operations. During
a refresh cycle, an external memory access cycle is held pending (ASTB, RD, WR, etc. are inactive), and during an
external memory access cycle, a refresh cycle is held pending.
If there is no overlapping with an external memory access operation, the refresh cycle is performed without affecting
CPU instruction execution.
630
Preliminary User’s Manual U13987EJ1V0UM00