UPD784938 Datasheet, PDF (370/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
(4) While an instruction that writes data to the compare register (CR2n: n = 0, 1) is executed, coincidence between CR2n,
to which the data is to be written, and timer counter 2 (TM2) is not detected. For example, if the contents of CR2n
do not change before and after the writing, the interrupt request is not generated even if the value of TM2 coincides
with the value of CR2n, nor does the timer output (TOn + 2: n + 2 = 2, 3) change.
Write data to CR2n when timer/event counter 2 is executing count operation in the manner that the contents of TM2
do not match the value of CR2n before and after writing (e.g., immediately after an interrupt request has been generated
because TM2 and CR2n have matched).
(5) Match between TM2 and compare register (CR2n: n = 0, 1) is detected only when TM2 is incremented. Therefore,
the interrupt request is not generated and timer output (TOn + 2 : n + 2 = 2, 3) does not change even if the same value
as TM2 is written to CR2n.
(6) During PPG output, if the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt,
the value of the compare register (CR2n: n = 0, 1) cannot be rewritten by interrupt processing that is performed on
match between timer counter 2 (TM2) and compare register (CR2n). Use another method (for example, to poll the
interrupt request flags by software with all the interrupts masked).
(7) The output level of the TOn (n = 2, 3) when the timer output is disabled (ENTOn = 0: n = 2, 3) is the inverse value
of the value set to the ALVn (n = 2, 3) bits. Note, therefore, that an active level is output when the timer output is disabled
with the PWM output function or PPG output function selected.
(8) When using timer/event counter 2 as an external event counter, the status where no valid edge is input cannot be
distinguished from the status where only one valid edge has been input, by using TM2 alone (refer to Figure 11-62),
because the contents of TM2 are 0 in both the cases. To make a distinction, use the interrupt request flag of INTP2,
as shown in Figure 11-63 (the INTP2 pin is multiplexed with the CI pin and both the functions can be used at the same
time).
Figure 11-62. Example of the Case where External Event Counter does Not Distinguish between One Valid
Edge Input and No Valid Edge Input
CI
TM2 0
0
Cannot be
distinguished
Count start
1
2
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