UPD784938 Datasheet, PDF (414/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 16 A/D CONVERTER
(3) A/D conversion time
The A/D conversion time is determined by the system clock frequency (fCLK) and the FR bit of the A/D converter mode
register (ADM).
The A/D conversion time includes the entire time required for one A/D conversion operation, and the sampling time
is also included in the A/D conversion time.
These values are shown in Table 16-1.
Table 16-1. A/D Conversion Time
System Clock (fCLK) Range
2 MHz ≤ fCLK ≤ 16 MHz
2 MHz ≤ fCLK ≤ 16 MHz
FR Bit
0
1
Conversion Time
180/fCLK
(11.3 µs to 90 µs)
120/fCLK
(7.5 µs to 60 µs)
Sampling Time
36/fCLK
(2.3 µs to 18 µs)
24/fCLK
(1.5 µs to 12 µs)
(4) A/D converter operation modes
There are two A/D converter operation modes, scan mode and select mode. These modes are selected according
to the setting of bit 0 (MS) of the A/D converter mode register (ADM). In addition, scan mode 0 or 1 can be selected
by bit 5 (SCMD) of the ADM.
Operation in either mode continues until the ADM is rewritten.
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Preliminary User’s Manual U13987EJ1V0UM00