UPD784938 Datasheet, PDF (32/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

LIST OF FIGURES (10/12)
Figure No.
Title
Page
20-22
20-23
20-24
20-25
20-26
20-27
20-28
Unit Status Register (USR) Format ............................................................................................................ 492
Broadcasting Communication Flag Operation Example ............................................................................ 493
Interrupt Status Register (ISR) Format ....................................................................................................... 494
Slave Status Register (SSR) Format .......................................................................................................... 498
Success Count Register (SCR) Format ...................................................................................................... 499
Communication Count Register (CCR) Format .......................................................................................... 499
Configuration of Interrupt Control Block ..................................................................................................... 500
21-1
21-2
21-3
21-4
Clock Output Function Configuration .......................................................................................................... 511
Clock Output Mode Register (CLOM) Format ............................................................................................ 513
Clock Output Operation Timing ................................................................................................................... 514
One-Bit Output Port Operation .................................................................................................................... 515
22-1
22-2
22-3
22-4
22-5
22-6
External Interrupt Mode Register 0 (INTM0) Format ................................................................................. 518
External Interrupt Mode Register 1 (INTM1) Format ................................................................................. 519
Sampling Clock Selection Register (SCS0) Format ................................................................................... 520
Edge Detection for Pins P20, P25, and P26 .............................................................................................. 521
P21 Pin Edge Detection .............................................................................................................................. 522
Edge Detection for Pins P22 to P24 ........................................................................................................... 523
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
Interrupt Control Registers (××ICn) ............................................................................................................. 534
Interrupt Mask Register (MK0, MK1) Format ............................................................................................. 538
In-Service Priority Register (ISPR) Format ................................................................................................ 540
Interrupt Mode Control Register (IMC) Format .......................................................................................... 541
Watchdog Timer Mode Register (WDM) Format ........................................................................................ 542
Program Status Word (PSWL) Format ....................................................................................................... 543
Context Switching Operation by Execution of a BRKCS Instruction ......................................................... 544
Return from BRKCS Instruction Software Interrupt (RETCSB instruction operation) .............................. 545
Non-Maskable Interrupt Request Acknowledgment Operations ................................................................ 547
Interrupt Acknowledgment Processing Algorithm ....................................................................................... 551
Context Switching Operation by Generation of an Interrupt Request ....................................................... 552
Return from Interrupt that Uses Context Switching by Means of RETCS Instruction .............................. 553
Examples of Servicing when Another Interrupt Request is Generated During Interrupt Service ............ 555
Examples of Servicing of Simultaneously Generated Interrupts ............................................................... 558
Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting ............................. 559
Differences between Vectored Interrupt and Macro Service Processing .................................................. 560
Macro Service Processing Sequence ......................................................................................................... 563
Operation at End of Macro Service when VCIE = 0 .................................................................................. 564
Operation at End of Macro Service when VCIE = 1 .................................................................................. 565
Macro Service Control Word Format .......................................................................................................... 566
Macro Service Mode Register Format ........................................................................................................ 567
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Preliminary User’s Manual U13987EJ1V0UM00