UPD784938 Datasheet, PDF (312/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
11.3 Timer/Event Counter 2 Control Registers
(1) Timer control register 1 (TMC1)
In TMC1 the timer/event counter 2 TM2/TM2W count operation is controlled by the high-order 4 bits (the low-order 4
bits control the count operation of timer/event counter 1, TM1/TM1W).
TMC1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of
TMC1 is shown in Figure 11-2.
RESET input clears TMC1 to 00H.
Figure 11-2. Timer Control Register 1 (TMC1) Format
7
6
5
4
3
2
1
TMC1 CE2 OVF2 CMD2 BW2 CE1 OVF1 0
0 Address After reset R/W
BW1 0FF5FH
00H
R/W
Remark The OVF2 bit is reset by software only.
Controls count operation of timer/event counter 1
TM1/TM1W (see Figure 10-2).
BW2
Timer/Event Counter 2 Bit Length
Specification
0 8-bit operation mode
1 16-bit operation mode
CMD2 TM2/TM2W Operation Mode Specificaton
0 Normal mode
1 One-shot mode
OVF2
TM2/TM2W Overflow Flag
0 No overflow
1
Overflow ^Note
Note 8-bit operating mode:
count up from FFH to 00H
In 16-bit operating mode:
count up from FFFFH to 0000H
CE2 TM2/TM2W Count Operation Control
0 Count operation stopped with count cleared
1 Count operation enabled
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Preliminary User’s Manual U13987EJ1V0UM00