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UPD784938 Datasheet, PDF (635/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers
CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
24.4.2 Operation
When the HLDE bit of the hold mode register (HLDM) is set (to 1), the bus hold function is enabled. When the bus hold
function is enabled, pins P66 and P67 operate as the HLDRQ and HLDAK pins respectively. The HLDRQ pin becomes
high-impedance, and the HLDAK pin outputs a low-level signal.
If a high-level signal is input to the HLDRQ pin when the bus hold function is enabled, at the end of the access operation
being executed the address bus (A8 to A19), address/data bus (AD0 to AD7), RD, WR, and ASTB pins are all set to high-
impedance, the HLDAK pin output level is driven high, and the hold mode is established.
While the HLDAK pin is high (in the hold mode) the µPD784938 does not use the local bus interface, and therefore an
external DMA controller, etc. is free to access the memory.
When the HLDRQ pin input level changes from high to low, the hold mode is released, the HLDAK pin level changes
from high to low, and then the µPD784938 resumes use of the local bus.
A transition to the hold mode is performed between bus cycles, and the instruction being executed may be suspended.
Also, if a transition to the hold mode is made during execution of an instruction that does not use the local bus interface
when a program is fetched from the external memory, the µPD784938 continues execution of prefetched instructions until
it comes to an instruction that uses the local bus interface, and suspends instruction execution when there are no more
prefetched instructions. When the hold mode is released, execution of the suspended instruction is resumed from the point
at which it was suspended.
When a program is fetched from the internal ROM or RAM, execution of instructions until it comes to an instruction that
uses the local bus interface continues.
Figure 24-21. Hold Mode Timing
ASTB
Hi-Z
A8 to A19
Hi-Z
AD0 to AD7
Hi-Z
Hi-Z
RD
WR
Hi-Z
HLDRQ
HLDAK
Preliminary User’s Manual U13987EJ1V0UM00
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