UPD784938 Datasheet, PDF (390/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 13 WATCHDOG TIMER
13.3 Operation
13.3.1 Count operation
The watchdog timer is cleared, and the count started, by setting (to 1) the RUN bit of the watchdog timer mode register
(WDM). When overflow time specified by the WDM2 and WDM1 bits of WDM has elapsed after the RUN bit has been set
(to 1), a non-maskable interrupt (INTWDT) is generated.
If the RUN bit is set (to 1) again before the overflow time elapses, the watchdog timer is cleared and the count operation
is started again.
13.3.2 Interrupt priorities
The watchdog timer interrupt (INTWDT) is a non-maskable interrupt. Other non-maskable interrupts are interrupts from
the NMI pin (NMI). The order of acknowledgment when an INTWDT interrupt and NMI interrupt are generated simultaneously
can be specified by the setting of bit 4 of the watchdog timer mode register (WDM).
Even if INTWDT is generated while the NMI processing program is executed when NMI acknowledgement is specified
to take precedence, INTWDT is not acknowledged until completion of execution of the NMI processing program.
390
Preliminary User’s Manual U13987EJ1V0UM00