UPD784938 Datasheet, PDF (434/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Caution An asynchronous serial interface mode register (ASIM/ASIM2) rewrite should not be performed during
a transmit operation. If an ASIM/ASIM2 register rewrite is performed during a transmit operation,
subsequent transmit operations may not be possible (normal operation is restored by RESET input).
Software can determine whether transmission is in progress by using a transmission completion
interrupt (INTST/INTST2) or the interrupt request flag (STIF/STIF2) set by INTST/INTST2.
(2) Asynchronous serial interface status register (ASIS), Asynchronous serial interface status register 2 (ASIS2)
ASIS and ASIS2 contain flags that indicate the error contents when a receive error occurs. Flags are set (to 1) when
a receive error occurs, and cleared (to 0) when data is read from the serial receive buffer (RXB/RXB2). If the next
data is received before RXB/RXB2 is read, the overrun error flag (OVE/OVE2) is set (to 1), and the other error flags
are cleared (to 0) (if there is an error in the next data, the corresponding error flag is set (to 1)).
These registers can be read only with an 8-bit manipulation instruction or bit manipulation instruction. The format of
ASIS and ASIS2 is shown in Figure 18-4.
RESET input clears these registers to 00H.
Figure 18-4. Format of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial
Interface Status Register 2 (ASIS2)
7
6
5
4
3
2
1
0 Address After reset R/W
ASIS
0
0
0
0
0
PE FE OVE 0FF8AH
00H
R
ASIS2 0
0
0
0
0 PE2 FE2 OVE2 0FF8BH
00H
R
Overrun error flag
1 Next receive completed before data is
read from receive buffer
Framing error flag
1 Stop bit not detected
Parity error flag
1 Transmit data parity specification and
receive data parity do not match
Caution The serial receive buffer (RXB/RXB2) must be read even if there is a receive error. If RXB/RXB2 is not
read, an overrun error will occur when the next data is received, and the receive error state will continue
indefinitely.
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Preliminary User’s Manual U13987EJ1V0UM00