UPD784938 Datasheet, PDF (244/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
(3) Stopping PWM output
If timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0) during PWM signal
output, the active level is output.
Figure 9-22. When Timer/Event Counter 0 is Stopped During PWM Signal Output
FFFFH
FFFFH
TM0
count value
0H
CR00
CR00
TO0
Remark ALV0 = 1
Caution The output level of the TOn (n = 0, 1) pin when timer output is disabled (ENTOn = 0: n = 0, 1) is the inverse
of the value set in ALVn (n = 0, 1) bit. Caution is therefore required as the active level is output when timer
output is disabled when the PWM output function has been selected.
244
Preliminary User’s Manual U13987EJ1V0UM00