UPD784938 Datasheet, PDF (218/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
(5) External event counter
Counts the clock pulses input from the external interrupt request input pin (INTP3).
The clocks that can be input to timer/event counter 0 are shown in Table 9-4.
Table 9-4. Timer/Event Counter 0 Pulse Width Measurement Time
Maximum frequency
Minimum pulse width
(High and low levels)
When Counting One Edge
fCLK/6 (2.10 MHz)
3/fCLK (0.24 µs)
When Counting Both Edges
fCLK/6 (2.10 MHz)
3/fCLK (0.24 µs)
( ): When fCLK = 12.58 MHz
9.2 Configuration
Timer/event counter 0 consists of the following registers:
• Timer counter (TM0) × 1
• Compare register (CR00, CR01) × 2
• Capture register (CR02) × 1
The block diagram of timer/event counter 0 is shown in Figure 9-1.
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Preliminary User’s Manual U13987EJ1V0UM00