UPD784938 Datasheet, PDF (250/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
(4) Stopping PPG output
If timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0) during PPG signal
output, the active level is output irrespective of the output level at the time it was stopped.
Figure 9-28. When Timer/Event Counter 0 is Stopped During PPG Signal Output
CR01
CR01
TM0
count value
0H
CR00
CR00
TO0
Caution The output level of the TOn (n = 0, 1) pin when timer output is disabled (ENTOn = 0: n = 0, 1) is the inverse
of the value set in ALVn (n = 0, 1) bit. Caution is therefore required as the active level is output when timer
output is disabled when the PPG output function has been selected.
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Preliminary User’s Manual U13987EJ1V0UM00