UPD784938 Datasheet, PDF (401/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 15 PWM OUTPUT UNIT
15.3.4 PWM pulse width rewrite cycle specification
The start of PWM output and pulse width changes are performed in synchronization either with every 16 PWM pulse
cycles (2¹²/fPWMC) or with every PWM pulse cycle (2⁸/fPWMC). This PWM pulse width rewrite cycle specification is performed
by means of the SYNn bits of the PWM control register (PWMC).
When the SYNn bit is cleared (to 0), a pulse width change is performed every 16 PWM pulse cycles (2¹²/fPWMC). It therefore
takes a maximum of 2¹² clocks (326 µs when fPWMC = 12.58 MHz) until a pulse of a width corresponding to the data written
in the PWM modulo register (PWMn: n = 0, 1) is output. An example of the PWM output timing at this time is shown in
Figure 15-6.
When the SYNn bit is set (to 1), on the other hand, a pulse width change is performed every PWM pulse cycle (2⁸/fPWMC).
In this case, it takes a maximum of 2⁸ clocks (20.4 µs when fPWMC = 12.58 MHz) until a pulse of a width corresponding to
the data written in the PWMn is output.
However, caution is required since, if the PWM pulse rewrite cycle is specified as every 2⁸/fPWMC, (if the SYNn bit is set
(to 1)), the obtained PWM pulse precision is between 8 bits and 12 bits, and is lower than when the PWM pulse rewrite
cycle is specified as 2¹²/fPWMC.
An example of the PWM output timing when the rewrite timing is 2⁸/fPWMC is shown in Figure 15-7.
Figure 15-6. PWM Output Timing Example 1 (PWM pulse width rewrite cycle = 2¹²/fPWMC)
16 PWM
pulse cycles
16 PWM
pulse cycles
PWM
output pin
PWMn
contents
n
PWM
output
enabled
m
PWMn
rewrite
PWM pulse width
switching timing
PWM pulse width
switching timing
PWM pulse width
switching timing
Cautions 1. Pulse width rewriting is performed every PWM pulse cycle.
2. The PWM pulse precision is 12 bits.
Preliminary User’s Manual U13987EJ1V0UM00
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