UPD784938 Datasheet, PDF (520/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 22 EDGE DETECTION FUNCTION
22.1.2 Sampling clock selection register (SCS0)
SCS0 specifies the sampling clock (fSMP) for digital noise elimination performed on pin P21.
SCS0 can be read or written to with an 8-bit manipulation instruction. The format of SCS0 is shown in Figure 22-3.
RESET input clears SCS0 to 00H.
Figure 22-3. Sampling Clock Selection Register (SCS0) Format
7
6
5
4
3
2
1
0 Address After reset R/W
SCS0 0
0
0
0
0
0 SCS01 SCS00 0FFA4H 00H R/W



fXX = 12.58 MHz
fCLK = 12.58 MHz



SCS01 SCS00 Sampling
Clock (fSMP)
Pulse Width
Eliminated
as Noise
Minimum
Pulse Width
Recognized
as Signal
0
0 fCLK
0
1 fXX/32
1
0 fXX/64
1
1 fXX/128
2/fCLK
(159 ns)
64/fXX
(5.1 µ s)
128/fXX
(10.2 µs)
256/fXX
(20.3 µ s)
3/fCLK
(239 ns)
96/fXX
(7.7 µ s)
192/fXX
(15.3 µ s)
384/fXX
(30.5 µ s)
520
Preliminary User’s Manual U13987EJ1V0UM00