UPD784938 Datasheet, PDF (82/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 3 CPU ARCHITECTURE
3.6 µPD78F4938 Memory Mapping
The memory size switching register (IMS) specifies the internal memory size. With the µPD78F4938, users are able to select
the internal memory capacity using the IMS so that the same memory map as that of mask ROM versions with a different internal
memory capacity can be achieved.
The IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to FFH.
Figure 3-6. Internal Memory Size Switching Register (IMS)
Address: 0FFFCCH
7
6
IMS
1
1
After reset: FFH
W/R
5
4
3
ROM1 ROM0
1
2
1
0
1
RAM1 RAM0
ROM1
0
0
1
1
ROM0
Internal ROM Capacity Selection
0 256 Kbytes
1 96 Kbytes
0 128 Kbytes
1 192 Kbytes
RAM1
0
0
1
1
RAM0
Internal RAM Capacity Selection
0 10,240 bytes
1 5,120 bytes
0 6,656 bytes
1 8,192 bytes
Caution The IMS is not contained in mask ROM products (µPD784935, 784936, 784937, 784938).
The IMS setting to obtain the same memory map as mask ROM products are shown in Table 3-3.
Table 3-3. Internal Memory Size Switching Register (IMS) Setting Value
Mask ROM Product
µPD784935
µPD784936
µPD784937
µPD784938
IMS Setting Value
DDH
EEH
FFH
CCH
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Preliminary User’s Manual U13987EJ1V0UM00