UPD784938 Datasheet, PDF (238/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.7.1 Basic operation
Setting (to 1) the ENTOn (n = 0, 1) bit of the timer output control register (TOC) enables timer output (TOn: n = 0, 1) to be
varied at a timing in accordance with the settings of MOD0, MOD1, and CLR01 bits of capture/compare control register 0 (CRC0)
and the one-shot pulse output control register (OSPC).
Clearing (to 0) ENTOn sets the TOn to a fixed level. The fixed level is determined by the ALVn (n = 0, 1) bit of the TOC. The
level is high when ALVn is 0, and low when 1.
9.7.2 Toggle output
Toggle output is an operation mode in which the output level is inverted each time the compare register (CR00/CR01) value
coincides with the timer counter 0 (TM0) value. The output level of timer output (TO0) is inverted by a match between CR00
and TM0, and the output level of TO1 is inverted by a match between CR01 and TM0.
When timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0), the inactive level
(ALVn: n = 0, 1) is output.
Figure 9-16. Toggle Output Operation
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
TM0
count value
0H
ENTO0
TO0 output
(ALV0 = 1)
CR01 value
CR00 value
CR01 value
CR00 value
CR01 value
CR00 value
CR01 value
CR00 value
Instruction
execution
Instruction Instruction
execution execution
ENTO1
TO1 output
(ALV1 = 0)
Instruction
execution
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Preliminary User’s Manual U13987EJ1V0UM00