UPD784938 Datasheet, PDF (319/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
11.4.2 Clear operation
(1) Clear operation after match with compare register and capture operation
Timer counter 2 (TM2) can be cleared automatically after a match with the compare register (CR2n: n = 0, 1) and a
capture operation. When a clearance source arises, TM2 is cleared to 0H on the next count clock. Therefore, even
if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count
clock arrives.
Figure 11-8. TM2 Clearance by Match with Compare Register (CR20/CR21)
Count clock
TM2
n-1
n
0
1
Compare register
n
(CR2n)
Count clock
TM2 and CR2n match Cleared here
Figure 11-9. TM2 Clearance after Capture Operation
TM2
n-1
n
0
1
2
INTP1
TM2 is captured
in CR22 here
Cleared here
(2) Clear operation by CE2 bit of timer control register 1 (TMC1)
TM2 is also cleared when the CE2 bit of the TMC1 is cleared (to 0) by software. The clear operation is performed
immediately after clearance (to 0) of the CE2 bit.
Preliminary User’s Manual U13987EJ1V0UM00
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