UPD784938 Datasheet, PDF (552/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.7.1 Vectored interrupt
When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and program
counter (PC) are saved in that order to the stack, the IE flag is cleared (to 0) (the interrupt disabled state is set), and the
in-service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (to 1). Also, data
in the vector table predetermined for each interrupt request is loaded into the PC, and a branch is performed. The return
from a vectored interrupt is performed by means of the RETI instruction.
Caution When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be used
to return from the interrupt. Subsequent interrupt acknowledgment will not be performed normally
if a different instruction is used.
23.7.2 Context switching
Initiation of the context switching function is enabled by setting (to 1) the context switching enable flag of the interrupt
control register.
When an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified
by 3 bits of the lower address (even address) of the corresponding vector table address is selected.
The vector address stored beforehand in the selected register bank is transferred to the program counter (PC), and at
the same time the contents of the PC and program status word (PSW) up to that time are saved in the register bank and
a branch is made to the interrupt service program.
Figure 23-11. Context Switching Operation by Generation of an Interrupt Request
Vector table
3 Register bank switching
(RBS0 to RBS2 ← n)
n
0000B
7 Transfer
PC19 to 16
PC15 to 0
Register bank n (n = 0 to 7)
A
X
6 Exchange
2 Save
(temporary
register
bits 8 to 11)
5 Save
V
Temporary register
U
T
1 Save
W
B
C
R5
R4
R7
R6
VP
UP
D
E
H
L
( ) 4 RSS ← 0
IE ← 0
Register bank
(0 to 7)
PSW
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