UPD784938 Datasheet, PDF (332/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
11.8.1 Basic operation
Setting (to 1) the ENTOn (n = 2, 3) bit of the timer output control register (TOC) enables timer output (TOn: n = 2, 3)
to be varied at a timing in accordance with the settings of MOD0, MOD1, and CLR21 bits of capture/compare control register
2 (CRC2).
Clearing (to 0) ENTOn sets the TOn to a fixed level. The fixed level is determined by the ALVn (n = 2, 3) bit of the TOC.
The level is high when ALVn is 0, and low when 1.
11.8.2 Toggle output
Toggle output is an operation mode in which the output level is inverted each time the compare register (CR20/CR21)
value coincides with the timer counter 2 (TM2) value. The output level of timer output (TO2) is inverted by a match between
CR20 and TM2, and the output level of timer output (TO3) is inverted by a match between CR21 and TM2.
When timer/event counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1), the inactive
level (ALVn: n = 0, 1) is output.
Figure 11-21. Toggle Output Operation
FFH
FFH
FFH
FFH
FFH
TM2
count value
0H
ENTO0
TO2 output
(ALV2 = 1)
CR21 value
CR20 value
CR21 value
CR20 value
CR21 value
CR20 value
CR21 value
CR20 value
Instruction
execution
Instruction execution Instruction execution
ENTO3
Instruction execution
TO3 output
(ALV3 = 0)
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Preliminary User’s Manual U13987EJ1V0UM00