UPD784938 Datasheet, PDF (660/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 26 RESET FUNCTION
Table 26-2. Hardware Status After Reset (2/2)
Hardware
Clock output function (CLOM)
Watch timer mode register (WM)
Memory extension mode register (MM)
Programmable wait control registers
PWC1
PWC2
Refresh function
Refresh mode register (RFM)
Refresh area specification register (RFA)
Hold mode register (HLDM)
Interrupts
Interrupt control registers (PIC0, PIC1, PIC2, PIC3, PIC4, PIC5, CIC00,
CIC01, CIC10, CIC11, CIC20, CIC21, CIC30, ADIC, SERIC, SRIC,
STIC, SERIC2, SRIC2, STIC2, CSIIC, CSIIC1, CSIIC2, IEIC1, IEIC2,
WIC, CSIIC3)
Interrupt mask registers
MK0
MK1
In-service priority register (ISPR)
Interrupt mode control register (IMC)
External interrupt mode registers (INTM0, INTM1)
Sampling clock selection register (SCS0)
Standby control register (STBC)
Oscillation stabilization time specification register (OSTS)
Internal memory size switching register (IMS)
IEBus controller
Bus control register (BCR)
Unit address register (UAR)
Slave address register (SAR)
Partner address register (PAR)
Control data register (CDR)
Telegraph-length register (DLR)
Data register (DR)
Unit status register (USR)
Interrupt status register (ISR)
Slave status register (SSR)
Success count register (SCR)
Communication count register (CCR)
State After Reset
00H
00H
20H
AAH
AAAAH
00H
00H
00H
43H
FFFFH
FFH
00H
00H
00H
00H
30H
00H
FFH
00H
0000H
01H
00H
41H
01H
20H
660
Preliminary User’s Manual U13987EJ1V0UM00