UPD784938 Datasheet, PDF (322/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
The TM2 count operation is controlled by the CE2 bit of the timer control register 1 (TMC1) in the same way as with
the basic operation.
When the CE2 bit is set (to 1) by software, the contents of TM2 are set to 0H and the count-up operation is started on
the initial count clock.
When the CE2 bit is cleared (to 0) by software during a TM2 count operation, the contents of TM2 are set to 0H immediately
and the stopped state is entered. The TM2 count operation is not affected if the CE2 bit is set (to 1) by software again
when it is already set (to 1).
Caution When timer/event counter 2 is used as an external event counter, it is not possible to distinguish
between the case where there is no valid edge input at all and the case where there is a single valid
edge input using timer counter 2 (TM2) alone (see Figure 11-12), since the contents of TM2 are 0 in
both cases. If it is necessary to make this distinction, the INTP2 interrupt request flag should be used
(the INTP2 pin and CI pin have a dual function, and both functions can be used at the same time). An
example is shown in Figure 11-13.
Figure 11-12. Example of the Case where the External Event Counter does Not Distinguish between One
Valid Edge Input and No Valid Edge Input
INTP2/CI
TM2 0
0
No distinction made
Count start
1
2
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Preliminary User’s Manual U13987EJ1V0UM00