UPD784938 Datasheet, PDF (456/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
18.5 Cautions
(1) An asynchronous serial interface mode register (ASIM) rewrite should not be performed during a transmit operation.
If an ASIM rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal
operation is restored by RESET input).
Software can determine whether transmission is in progress by using a transmission completion interrupt (INTST) or
the interrupt request flag (STIF) set by INTST.
(2) After RESET input the serial transmit shift register (TXS) is emptied but a transmission completion interrupt is not
generated. A transmit operation can be started by writing transmit data to the TXS.
(3) The serial receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun error will
occur when the next data is received, and the receive error state will continue indefinitely.
(4) The contents of the asynchronous serial interface status register (ASIS) are cleared (to 0) by reading the serial receive
buffer (RXB) or by reception of the next data. If you want to find the details of an error, therefore, ASIS must be read
before reading RXB.
(5) The baud rate generator control register (BRGC) should not be written to during communication. If a write instruction
is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock
may be disrupted, preventing normal communication from continuing.
(6) To specify the transfer bit order with CSIM1 and CSIM2 (bit 2 manipulation), do not set the CTXE and CRXE bits at
the same time. If these bits are specified at the same time, the bit transfer order may not be as specified.
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Preliminary User’s Manual U13987EJ1V0UM00