UPD784938 Datasheet, PDF (451/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 18-15. Format of Baud Rate Generator Control Register (BRGC) and
Baud Rate Generator Control Register 2 (BRGC2)
7
6
5
4
3
2
1
0 Address After reset R/W
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 0FF90H
00H
R/W
BRGC2 TPS23 TPS22 TPS21 TPS20 MDL23 MDL22 MDL21 MDL20 0FF91H
00H
R/W
fPRS: Prescaler output selection clock
MDL3 MDL2 MDL1 MDL0 _{k Baud Rate Generator Input}
MDL23 MDL22 MDL21 MDL20
Clock^{Note 1}
0
0
0
0
0 fPRS/16
0
0
0
1
1 fPRS/17
0
0
1
0
2 fPRS/18
0
0
1
1
3 fPRS/19
0
1
0
0
4 fPRS/20
0
1
0
1
5 fPRS/21
0
1
1
0
6 fPRS/22
0
1
1
1
7 fPRS/23
1
0
0
0
8 fPRS/24
1
0
0
1
9 fPRS/25
1
0
1
0 10 fPRS/26
1
0
1
1 11 fPRS/27
1
1
0
0 12 fPRS/28
1
1
0
1 13 fPRS/29
1
1
1
0 14 fPRS/30
1
1
1
1
15 fPRS^{Note 2}
Notes 1. Only fPRS/16 can be selected when ASCK/ASCK2 input is used.
2. Can only be used in 3-wire serial I/O mode.
fXX: Oscillator frequency or external clock input
TPS3 TPS2 TPS1 TPS0 _n
TPS23 TPS22 TPS21 TPS20
0
0
0
00
12-Bit Prescaler Tap
Selection (fPRS)
fXX/2
fASCK/2^Note
0
0
0
1
1 fXX/4
fASCK/4
0
0
1
0
2 fXX/8
fASCK/8
0
0
1
1
3 fXX/16
fASCK/16
0
1
0
0
4 fXX/32
fASCK/32
0
1
0
1
5 fXX/64
fASCK/64
0
1
1
0
6 fXX/128 fASCK/128
0
1
1
1
7 fXX/256 fASCK/256
1
0
0
0
8 fXX/512 fASCK/512
1
0
0
1
9 fXX/1,024 fASCK/1,024
1
0
1
0 10 fXX/2,048 fASCK/2,048
1
0
1
1 11 fXX/4,096 fASCK/4,096
Other than the above
Setting prohibited
Note Can not be selected when the value set in bits MDL3 to MDL0,
k = 15.
Preliminary User’s Manual U13987EJ1V0UM00
451