UPD784938 Datasheet, PDF (486/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
Caution When the CPU is busy with other processing, slave reception can be disabled by resetting this
flag and returning NACK with the acknowledge bit of the control field. Therefore, when this flag
is reset, individual communication can be disabled, but broadcasting communication cannot.
Furthermore, during individual communication, start interrupt (INTIE2) is generated. When CPU
processing is prioritized (in case neither reception nor transmission are to be performed), reset
ENIEBUS (communication enable flag) and stop the IEBus unit. Also, when returning to the
enabled status from the disabled status, the operation becomes effective from the next new
frame.
(2) Unit address register (UAR)
This register sets the unit address of an IEBus unit. This register must be always set before starting communication.
Figure 20-12. Unit Address Register (UAR) Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address After reset R/W
UAR 0 0 0 0
0FFB2H 0000H R/W
Sets unit address (12 bits)
(3) Slave address register (SAR)
During master request, the value of this register is reflected on the value of the transmit data in the slave address field.
This register must be always set before starting communication.
Figure 20-13. Slave Address Register (SAR) Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address After reset R/W
SAR 0 0 0 0
0FFB4H 0000H R/W
Sets slave address (12 bits)
(4) Partner address register (PAR)
[During slave unit]
The value of the receive data in the master address field (address of the master unit) is written to this register.
If a request “4H” to read the lock address (low-order 8 bits) is received from the master, the CPU must read the
value of this register, and write the data of the low-order 8 bits to the data register (DR).
If a request “5H” to read the lock address (high-order 4 bits) is received from the master, the CPU must read the
value of this register and write the data of the high-order 4 bits to DR.
Figure 20-14. Partner Address Register (PAR) Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address After reset R/W
PAR 0 0 0 0
0FFB6H 0000H R
Sets partner address (12 bits)
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Preliminary User’s Manual U13987EJ1V0UM00