UPD784938 Datasheet, PDF (438/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
18.2.6 Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), receive operations are enabled
and sampling of the RxD input pin is performed.
RxD input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by ASIM and band
rate generator control register (BRGC).
When the RxD pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal
is output on the m'th count. If the RxD pin input is low when sampled again by this start timing signal, the input is recognized
as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. When the
character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends.
When reception of one data frame ends, the receive data in the shift register is transferred to the serial receive buffer,
RXB, and a reception completion interrupt (INTSR) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB. If bit 1 (ISRM) of the ASIM
was cleared (to 0) when the error occurred,
INTSR is generated. If the ISRM was set (to 1), INTSR is not generated.
If the RXE bit is cleared (to 0) during a receive operation, the receive operation is stopped immediately. In this case
the contents of RXB and ASIS are not changed, and no INTSR or INTSER interrupt is generated.
Figure 18-7. Asynchronous Serial Interface Reception Completion Interrupt Timing
RxD (input)
INTSR
D0 D1 D2
START
STOP
D6 D7 Parity
Caution The serial receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an
overrun error will occur when the next data is received, and the receive error state will continue
indefinitely.
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Preliminary User’s Manual U13987EJ1V0UM00