UPD784938 Datasheet, PDF (110/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 4 CLOCK GENERATOR
4.3 Clock Generator Operation
4.3.1 Clock oscillator
(1) When using crystal/ceramic oscillation
The clock oscillator starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set by
the standby control register (STBC). Oscillation is resumed when the STOP mode is released.
(2) When using external clock
The clock oscillator supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input.
4.3.2 Divider
The divider performs 1/1, 1/2, 1/4, or 1/8 scaling of the clock oscillator output, and supplies the resulting clock to the CPU,
watchdog timer, noise elimination circuit, clocked serial interface (CSI), A/D converter, PWM, interrupt control circuit, and local
bus interface. The division ratio is specified by the CK0 and CK1 bits of the standby control register (STBC).
Controlling the division ratio to match the speed required by the CPU enables the overall power consumption to be reduced.
Also, the operating speed can be selected to match the supply voltage.
When RESET is input, the lowest speed (1/8) is selected.
If the division ratio of the divider circuit is changed, the maximum time shown in Table 4-1 is required to change the division
ratio, depending on the clock selected before change.
Instruction execution continues even while the division ratio is changed, and the clock is supplied with the previous division
ratio until the division ratio has been completely changed.
Table 4-1. Time Required to Change Division Ratio
Previous Division Ratio
None
1/2
1/4
1/8
Maximum Time Required for Change
11/fXX
12/fXX
8/fXX
8/fXX
110
Preliminary User’s Manual U13987EJ1V0UM00