UPD784938 Datasheet, PDF (89/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 3 CPU ARCHITECTURE
Figure 3-10. Data Saved to Stack Area
PUSH sfr instruction
stack
SP
↓
SP– 1
SP←SP– 1
PUSH sfrp instruction
stack
SP
↓
SP– 1
↓
SP– 2
SP←SP– 2
Upper byte
Lower byte
PUSH PSW instruction
stack
PUSH rg instruction
stack
SP
↓
SP– 1
↓
SP– 2
PSWH7 to _Undefined
PSWH4
PSWL
SP←SP– 2
SP
↓
SP– 1
↓
SP– 2
↓
SP– 3
SP←SP– 3
Upper byte
Middle byte
Lower byte
CALL, CALLF, CALLT instruction
stack
Vectored interrupt
stack
SP
↓
SP– 1
↓
SP– 2
↓
SP– 3
Undefined
PC19 to
PC16
PC15 to PC8
PC7 to PC0
SP←SP– 3
SP
↓
SP– 1
↓
SP– 2
↓
SP– 3
↓
SP– 4
PSWH7 to _{PC19 to}
PSWH4
PC16
PSWL
PC15 to PC8
PC7 to PC0
SP←SP– 4
PUSH post, PUSHU post instruction
(in case of PUSH AX, RP2, RP3)
stack
SP
↓
SP– 1
↓
SP– 2
↓
SP– 3
↓
SP– 4
↓
SP– 5
↓
SP– 6
SP←SP– 6
R7

 RP3
R6

R5

 ^RP2
R4

A

 ^AX
X

Preliminary User’s Manual U13987EJ1V0UM00
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