UPD784938 Datasheet, PDF (433/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 18-3. Format of Asynchronous Serial Interface Mode Register (ASIM) and Asynchronous Serial
Interface Mode Register 2 (ASIM2)
7
6
5
4
3
ASIM TXE RXE PS1 PS0 CL
2
1
0 Address After reset R/W
SL ISRM SCK 0FF88H
00H
R/W
ASIM2 TXE2 RXE2 PS21 PS20 CL2 SL2 ISRM2 SCK2 0FF89H
00H
R/W
SCK Specification of Input Clock to Baud Rate
SCK2
Generator
0 External clock input (ASCK, ASCK2)
1 Internal clock (fxx)
ISRM
ISRM2
Specification of Enabling/Disabling of
Reception Completion Interrupt
Generation in Case of Receive Error
0 Enabled
1 Disabled
SL
Stop Bit Length Specification
SL2
(Transmission Only)
0 1 bit
1 2 bits
CL
Data Character Length Specification
CL2
0 7 bits
1 8 bits
PS1 PS0
PS21 PS20
Parity Bit Specification
0
0 No parity
0
1 Transmission = 0 parity addition
Reception = Parity error not
generated
1
0 Odd parity
1
1 Even parity
TXE RXE
TXE2 RXE2
Transmit/Receive Operation
0
0 Transmission/reception disabled,
or 3-wire serial I/O mode
0
1 Reception enabled
1
0 ^{Transmission enabled}
1
1 Transmission/reception enabled
Preliminary User’s Manual U13987EJ1V0UM00
433