UPD784938 Datasheet, PDF (546/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.5 Operand Error Interrupt Acknowledgment Operation
An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand
of a “MOV STBC, #byte instruction ”,“ LOCATION instruction” or a “MOV WDM, #byte instruction” does not match the 4th
byte of the operand. Operand error interrupts cannot be disabled.
When an operand error interrupt is generated, the program status word (PSW) and the start address of the instruction
that caused the error are saved to the stack, the IE flag is cleared (to 0), the vector table value is loaded into the program
counter (PC), and a branch is performed (within the base area only).
As the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an
RETB instruction at the end of the operand error interrupt service program will result in generation of another operand error
interrupt. You should therefore either process the address in the stack or initialize the program by referring to 23.12
Restoring Interrupt Function to Initial State.
23.6 Non-Maskable Interrupt Acknowledgment Operation
Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be
acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non-
maskable interrupt of higher priority.
The relative priorities of non-maskable interrupts are set by the PRC bit of the watchdog timer mode register (WDM)
(see 23.3.5 Watchdog timer mode register (WDM)).
Except in the cases described in 23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending,
a non-maskable interrupt request is acknowledged immediately. When a non-maskable interrupt request is acknowledged,
the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (to
0), the in-service priority register (ISPR) bit corresponding to the acknowledged non-maskable interrupt is set (to 1), the
vector table contents are loaded into the PC, and a branch is performed. The ISPR bit that is set (to 1) is the NMIS bit
in the case of a non-maskable interrupt due to edge input to the NMI pin, and the WDTS bit in the case of watchdog timer
overflow.
When the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority
as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable
interrupt currently being executed are held pending. A pending non-maskable interrupt is acknowledge after completion
of the non-maskable interrupt service program currently being executed (after execution of the RETI instruction). However,
even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable
interrupt service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt
service program.
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Preliminary User’s Manual U13987EJ1V0UM00