UPD784938 Datasheet, PDF (533/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.3.1 Interrupt control registers
An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for
the corresponding interrupt request. The interrupt control register format is shown in Figure 23-1.
(1) Priority specification flags (××PR1/××PR0)
The priority specification flags specify the priority on an individual interrupt source basis for the 25 maskable interrupts.
Up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. Among
maskable interrupt sources, level 0 is the highest priority.
If multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they are
acknowledged in default priority order.
These flags can be manipulated bit-wise by software.
RESET input sets all bits to “1”.
(2) Context switching enable flag (××CSE)
The context switching enable flag specifies that a maskable interrupt request is to be serviced by context switching.
In context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector
address stored beforehand in the register bank, and at the same time the current contents of the program counter (PC)
and program status word (PSW) are saved in the register bank.
Context switching is suitable for real-time processing, since execution of interrupt servicing can be started faster than
with normal vectored interrupt servicing.
This flag can be manipulated bit-wise by software.
(3) Macro service enable flag (××ISM)
The macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by
vectored interruption or context switching, or by macro service.
When macro service processing is selected, at the end of the macro service (when the macro service counter reaches
0) the macro service enable flag is automatically cleared (to 0) by hardware (vectored interrupt service/context switching
service).
This flag can be manipulated bit-wise by software.
RESET input sets all bits to “0”.
(4) Interrupt mask flag (××MK)
An interrupt mask flag specifies enabling/disabling of vectored interrupt servicing and macro service processing for
the interrupt request corresponding to that flag.
The interrupt mask contents are not changed by the start of interrupt service, etc., and are the same as the interrupt
mask register contents (see 23.3.2 Interrupt Mask Registers (MK0/MK1)).
Macro service processing requests are also subject to mask control, and macro service requests can also be masked
with this flag.
This flag can be manipulated by software.
RESET input sets all bits to “1”.
(5) Interrupt request flag (××IF)
An interrupt request flag is set (to 1) by generation of the interrupt request that corresponds to that flag. When the
interrupt is acknowledged, the flag is automatically cleared (to 0) by hardware.
This flag can be manipulated by software.
RESET input sets all bits to “0”.
Preliminary User’s Manual U13987EJ1V0UM00
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