UPD784938 Datasheet, PDF (647/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
25.4.2 STOP mode release
STOP mode is released by NMI input, INTP4 input, INTP5 input, INTW input, and RESET input.
Table 25-5. STOP Mode Release and Operations after Release
Release Source MK^{Note 1} ISM^{Note 2} IE^{Note 3}
State after Release
Operation after Release
RESET input
×
×
×
—
Normal reset operation
NMI pin input
×
×
×
• Non-maskable interrupt service
Interrupt request acknowledgment
program not being executed
• Low-priority non-maskable interrupt
service program being executed
• NMI pin input service program being
executed
• High-priority non-maskable interrupt
service program being executed
Execution of instruction after MOV
STBC, #byte instruction (interrupt
request that released STOP mode is
held pending^{Note 4})
INTP4/INTP5
0
0
1
• Interrupt service program not being
Interrupt request acknowledgment
pin input,
executed
INTW input
• Low-priority maskable interrupt service
program being executed
• PRSL bit^{Note 5} cleared (to 0) during
execution of priority level 3 interrupt
service program
• Same-priority maskable interrupt
service program being executed
(If PRSL bit^{Note 5} is cleared (to 0),
excluding execution of priority level 3
interrupt service program)
• High-priority interrupt service program
being executed
Execution of instruction after MOV
STBC, #byte instruction (interrupt
request that released STOP mode is
held pending^{Note 4})
0
0
0
—
1
0
×
—
STOP mode maintained
×
1
×
Notes 1. Interrupt mask bit in individual interrupt request source
2. Macro service enable flag in individual interrupt request source
3. Interrupt enable flag in program status word (PSW)
4. Pending interrupt requests are acknowledged when acknowledgment becomes possible.
5. Bit in interrupt mode control register (IMC)
Preliminary User’s Manual U13987EJ1V0UM00
647