UPD784938 Datasheet, PDF (507/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
20.6.5 Interval of occurrence of interrupt for IEBus control
Each control interrupt must occur at each point of communication and perform the necessary processing until the next
interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into
consideration.
The locations at which the following interrupts may occur are indicated by ↑ in the field where it may occur. ↑ does not
mean that the interrupt occurs at each of the points indicated by ↑. If an error interrupt (timing error, parity error, or ACK
error) occurs, the IEBus internal circuit is initialized. As a result, the following interrupt does not occur in that communication
frame.
(1) Master transmission
Start bit
t1 T
Communication
starts
Broad-
casting
Master address
P
Slave address
PA
Control
PA
Telegraph
lengh
PA
Data
PA
T
T
t2
T
AT
AT
t3
t4
P
Communication
starts
AT
U
t5
Data P A Data
T
U
t4
Data
T
PA
End of communication
End of frame
Remarks 1. T: timing error, P: parity error, A: ACK error, U: underrun error
: data set interrupt (INTIE1)
2. End of frame occurs at the end of 32-byte data.
Item
Communication starts – timing error
Communication starts – communication start interrupt
Communication start interrupt – ACK error
Communication start interrupt – end of communication
Data transmission – underrun error
(IEBus: @ 6-MHz operation)
Symbol
MIN.
Unit
t1
Approx. 97
µs
t2
Approx. 1,380
µs
t3
Approx. 16
µs
t4
Approx. 1,014
µs
t5
Approx. 390
µs
Preliminary User’s Manual U13987EJ1V0UM00
507