UPD784938 Datasheet, PDF (262/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.8.5 Operation as PPG output
In PPG output, pulses with the cycle and duty ratio determined by the values set in the compare registers (CR0n: n = 0, 1)
are output (see Figure 9-45).
The control register settings are shown in Figure 9-46, the setting procedure in Figure 9-47, and the procedure for varying
the duty in Figure 9-48.
Figure 9-45. Example of Timer/Event Counter 0 PPG Signal Output
TM0
count value
CR00
0H
Timer start
TO0
(when active-low)
CR01
CR00
CR01
CR00
CR01
Figure 9-46. Control Register Settings for PPG Output Operation
(a) Capture/compare control register 0 (CRC0)
7
6
5
4
3
2
1
0
CRC0 1
1
0
1
1
0
0
0
TM0 cleared by match of TM0 & CR01
TO0 = PPG output
(b) Timer output control register (TOC)
7
6
5
4
3
2
1
0
TOC
×
×
×
×
×
×
1
1
TO0 = active-low PPG signal output
TO0 PPG output enabled
(c) Port 3 mode control register (PMC3)
7
6
5
4
3
2
1
0
PMC3 ×
×
×
1
×
×
×
×
P34 pin set as TO0 output
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Preliminary User’s Manual U13987EJ1V0UM00