UPD784938 Datasheet, PDF (557/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
Figure 23-13. Examples of Servicing when Another Interrupt Request is Generated During Interrupt Service (3/3)
Main routine
Interrupt request q
(level 3)
EI
Interrupt
request r
(level 2)
q
EI
servicing
r
EI
servicing
s
EI
servicing
t servicing
Interrupt
request s
(level 1)
Interrupt
request t
(level 0)
EI
Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC register is set (to 1),
only macro service requests and non-
maskable interrupts generate nesting
beyond this.
If the PRSL bit of the IMC register is
cleared (to 0), level 3 interrupts can also be
nested during level 3 interrupt servicing
(see Figure 23-15).
Interrupt request u
(level 0)
u servicing
EI
Interrupt
request v
(level 0)
Interrupt
request w
(level 3)
w macro service
v servicing
Interrupt request x
(level 1)
Interrupt
request y^Note
(level 2)
Interrupt
request z^Note
(level 2)
x servicing
z servicing
y servicing
Even though the interrupt enabled state is
set during servicing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the macro
service request is acknowledged and
serviced irrespective of its level and even
though there is a peding interrupt with a
higher priority level.
Pending interrupt requests y and z are
acknowledged after servicing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.
Notes 1. Low default priority
2. High default priority
Remarks 1. “a” to “z” in the figure are arbitrary names used to differentiate between the interrupt requests and macro
service requests.
2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt requests.
Preliminary User’s Manual U13987EJ1V0UM00
557