UPD784938 Datasheet, PDF (444/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
18.3.3 Basic operation timing
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit
by bit in MSB-first or LSB-first order in synchronization with the serial clock.
MSB/LSB switching is specified by the DIR1 bit of the clock serial interface mode register (CSIM1).
Transmit data is output in synchronization with the fall of SCK1, and receive data is sampled on the rise of SCK1.
An interrupt request (INTCSI1) is generated on the 8th rise of SCK1.
When the internal clock is used as SCK1, SCK1 output is stopped on the 8th rise of SCK1 and SCK1 remains high until
the next data transmit or receive operation is started.
3-wire serial I/O mode timing is shown in Figure 18-12.
Figure 18-12. 3-Wire Serial I/O Mode Timing (1/2)
(a) MSB-first
SCK1^Note
SI1 (input)
SO1 (output)
1 2 34567 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI1
Transfer end
interrupt generation
Start of transfer synchronized with fall of SCK1 Note Master CPU: Output
Slave CPU: Input
Execution of instruction that writes to SIO1, etc.
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Preliminary User’s Manual U13987EJ1V0UM00