UPD784938 Datasheet, PDF (316/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
11.4 Timer Counter 2 (TM2) Operation
11.4.1 Basic operation
8-bit operation mode/16-bit operation mode control can be performed for timer/event counter 2 by means of bit 0 (BW2)
of timer control register 2 (TMC2)^Note.
In the timer/event counter 2 count operation, a count-up is performed using the count clock specified by the high-order
4 bits of prescaler mode register 1 (PRM1).
Count operation enabling/disabling is controlled by bit 3 (CE2) of TMC2 (timer/event counter 2 operation control is
performed by the high-order 4 bits of the timer control register 1 (TMC1). When the CE2 bit is set (to 1) by software, the
contents of TM2 are cleared to 0H on the first count clock, and then the count-up operation is performed.
When the CE2 bit is cleared (to 0) by software, TM2 becomes 0H immediately, and capture operations and match signal
generation are stopped.
If the CE2 bit is set (to 1) again when it is already set (to 1), the TM2 count operation is not affected (see Figure 11-
6 (b)).
TM2/TM2W is cleared to 0H when the count clock is input while the value of TM2 is FFH in the 8-bit operation mode
or while the value of TM2W is FFFFH in the 16-bit operation mode. At this time, OVF2 bit is set and the overflow signal
is sent to the output control circuit. OVF2 bit is cleared by software only. The count operation is continued.
When RESET is input, TM2 is cleared to 0H, and the count operation is stopped.
Note
Unless otherwise specified, the functions of timer counter 2 in the 8-bit operation mode are described hereafter.
In the 16-bit operation mode, TM2, CR20, CR21, and CR22 operate as TM2W, CR20W, CR21W, and CR22W,
respectively.
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Preliminary User’s Manual U13987EJ1V0UM00