UPD784938 Datasheet, PDF (251/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.7.5 Software triggered one-shot pulse output
In the software triggered one-shot pulse output mode, a one-shot pulse is output by software.
When the STn (n = 0, 1) bit of the one-shot pulse output control register (OSPC) is set (1), timer output pin (TOn: n = 0, 1)
is set to the active level. TOn then remains at the active level until the timer counter 0 (TM0) value and the compare register
(CR0n: n = 0, 1) value match, at which point TOn changes to the inactive level. TOn then remains at the inactive level until the
STn bit is set again. TOn can also be set to the inactive level by setting (to 1) the RTn bit (n = 0, 1), and in the same way, TOn
remains at the inactive level until the STn bit is set again.
TO0 and TO1 can be controlled independently.
An example of software triggered one-shot pulse output is shown in Figure 9-29.
When timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the TMC0, the level at the time was stopped is retained.
Figure 9-29. Example of Software Triggered One-Shot Pulse Output
FFFFH
Software trigger
Count start
0H
ST0
INTC00
ALV0
“1”
TO0
Active period
Inactive level output
Caution “1” should not be written to STn and RTn simultaneously.
Preliminary User’s Manual U13987EJ1V0UM00
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