UPD784938 Datasheet, PDF (302/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 10 TIMER/EVENT COUNTER 1
(4) While an instruction that writes data to the compare register (CR1n: n = 0, 1) is executed, coincidence between CR1n, to
which the data is to be written, and timer counter 1 (TM1) is not detected.
Write data to CR1n when timer/event counter 1 is executing counting operation in the timing that the contents of TM1 do
not coincide with the value of CR1n before and after writing (e.g., immediately after an interrupt request has been generated
because TM1 and CR1n have coincided).
(5) Coincidence between TM1 and compare register (CR1n: n = 0, 1) is detected only when TM1 is incremented. Therefore,
the interrupt request is not generated even if the same value as TM1 is written to CR1n.
(6) When timer/event counter 1 is used as an external event counter, it is not possible to distinguish between the case where
there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 1 (TM1)
alone (refer to Figure 10-31), since the contents of TM1 are 0 in both cases. If it is necessary to make this distinction, the
INTP3 interrupt request flag should be used. To make a distinction, use the interrupt request flag of INTP0, as shown in
Figure 10-32.
Figure 10-31. Example of the Case where the External Event Counter does Not Distinguish
between One Valid Edge Input and No Valid Edge Input
INTP0
TM1 0
0
Cannot be
distinguished
Count start
1
2
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Preliminary User’s Manual U13987EJ1V0UM00