UPD784938 Datasheet, PDF (449/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

UART reception
shift clock
Figure 18-14. Baud Rate Generator Block Diagram
5-bit counter
Clear
1/2
Match
Start bit detection
RESET
Internal bus
1/8
1/8
CSIM1, CSIM2
ASIM1, ASIM2
8
BRGC, BRGC2
Start bit detection
sampling clock
Clocked serial Asynchronous serial
interface mode interface mode
registers 1 & 2 registers 1 & 2
Baud rate generator
control register
CSCK1
SCK
RESET
Shift clock
for UART
transmission
& IOE
Selector 1/2 Selector
CSCK1
Match
5-bit counter
fPRS
Frequency
fXX
Selector
divider
Selector
BRGC write
RESET
P25/ASCK/SCK1,
P12/ASCK2/SCK2