UPD784938 Datasheet, PDF (499/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
(11) Success count register (SCR)
This register reads the count value of the counter that decrements the value set by the telegraph length register by
ACK in the data field. When the count value has reached “00H”, the communication end flag (ENDTRNS) is set.
Figure 20-26. Success Count Register (SCR) Format
7
6
5
4
3
2
1
0 Address After Reset R/W
SCR
0FFBEH 01H
R
Remaining Number of Communication Data Bytes
01H
1 byte
02H
2 bytes
20H
32 bytes
FFH
00H
255 bytes
0 byte (end of communication) or 256 bytes^Note
Note The bit length of the actual hard counter consists of 9 bits. When “00H” is read, it cannot be judged whether
the remaining number of communication data bytes is 0 (end of communication) or 256. Therefore, either the
communication end flag is used, or if “00H” is read when the first interrupt occurs at the beginning of
communication, the remaining number of communication data bytes is judged to be 256.
(12) Communication count register (CCR)
This register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes)
per frame specified in mode 1 and is decremented during the ACK period of the data field regardless of ACK/NACK.
When the count value has reached “00H”, the frame end flag (ENDFRAM) is set.
Figure 20-27. Communication Count Register (CCR) Format
7
6
5
4
3
2
1
0 Address After reset R/W
CCR
0FFBFH 20H
R
Number of transmitted bytes
• Preset value in mode 1 and maximum number of transmitted bytes per frame ... 20H (32 bytes)
Preliminary User’s Manual U13987EJ1V0UM00
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