UPD784938 Datasheet, PDF (650/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
25.5 IDLE Mode
25.5.1 IDLE mode setting and operating status
The IDLE mode is selected by setting (to 1) both the STP bit and the HLT bit of the standby control (STBC) register.
The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. IDLE
mode setting is therefore performed by means of the ”MOV STBC, #byte” instruction.
Caution If the IDLE mode is set when the condition to release the HALT mode is satisfied (refer to 25.3.2 HALT
mode release), the IDLE mode is not set, but the next instruction is executed or execution branches
to a vectored interrupt service program. To accurately set the IDLE mode, clear the interrupt request
before setting the IDLE mode.
Table 25-6. Operating States in IDLE Mode
Clock oscillator
Internal system clock
CPU
I/O lines
Peripheral functions
Internal RAM
Bus lines
RD, WR output
ASTB output
REFRQ output
HLDRQ input
HLDAK output
AD0 to AD7
A8 to A19
Oscillation continued
Stopped
Operation stopped
Retain state prior to IDLE mode setting
All operation excluding watch timer (WM3 = 1,
WM6 = 0) stopped^Note
Retained
High-impedance
High-impedance
High-impedance
High-impedance
Retained
High-impedance
Low level
Note A/D converter operation is stopped, but if the CS bit of the A/D converter mode register (ADM) is set, the current
consumption does not decrease.
Caution The CS bit of the A/D converter mode (ADM) register should be reset.
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Preliminary User’s Manual U13987EJ1V0UM00