UPD784938 Datasheet, PDF (621/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
24.2.3 Access waits
Access waits are inserted in the RD or WR signal low-level period, and extend the low-level period by 1/fCLK (80 ns: fCLK
= 12.58 MHz) per cycle.
There are two wait insertion methods, using either the programmable wait function that automatically inserts the preset
number of cycles, or the external wait function controlled by a wait signal from outside.
For wait cycle insertion control, the 1-Mbyte memory space is divided into eight as shown in Figure 24-11, and control
is specified for each space by means of the programmable wait control registers (PWC1/PWC2). Waits are not inserted
in accesses to internal ROM or internal RAM using high-speed fetches. In accesses to internal SFRs, waits are inserted
at the necessary times regardless of this specification.
If access operations are specified as being performed in the same number of cycles as for external ROM, waits are
inserted also in internal ROM accesses in accordance with the PWC1 settings.
If there is a space for which control by a wait signal from outside has been selected by means of the PWC1/PWC2, the
P66 pin operates as the WAIT signal input pin. After RESET input, the P66 pin operates as a general-purpose input/output
port.
Bus timing in the case of access wait insertion is shown in Figures 24-12 to 24-14.
Caution The external wait function cannot be used when the bus hold function is used.
Preliminary User’s Manual U13987EJ1V0UM00
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