UPD784938 Datasheet, PDF (235/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.6.2 Capture operations
Timer/event counter 0 performs capture operations in which the timer counter 0 (TM0) count value is fetched into the capture
register in synchronization with an external trigger, and retained there.
A valid edge detected from the input of the external interrupt request input pin (INTP3) is used as the external trigger (capture
trigger). The count value of TM0 in the process of being counted is fetched into the capture register (CR02) in synchronization
with the capture trigger, and is retained there. The contents of the CR02 are retained until the next capture trigger is generated.
The capture trigger valid edge is set by means of external interrupt mode register 1 (INTM1). If both rising and falling edges
are set as capture triggers, the width of pulses input from off-chip can be measured. Also, if a capture trigger is generated by
a single edge, the input pulse cycle can be measured.
See Figure 22-2 for details of the INTM1.
Figure 9-15. Capture Operation
FFFFH
TM0
count value
D0
0H
Count start
CE0 ← 1
INTP3
pin input
INTP3
interrupt request
Capture register
(CR02)
D1
D2
D0
D1
D2
OVF0
Remark Dn: TM0 count value (n = 0, 1, 2, ...)
CLR01 = 0
Preliminary User’s Manual U13987EJ1V0UM00
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