UPD784938 Datasheet, PDF (273/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 10 TIMER/EVENT COUNTER 1
(3) External event counter
Counts the clock pulses input from the external interrupt request input pin (INTP0).
The clocks that can be input to timer/event counter 1 are shown in Table 10-3.
Sampling Clock^Note
fCLK
fXX/32
fXX/64
fXX/128
Table 10-3. Timer/Event Counter 1 Pulse Width Measurement Time
( ): When fCLK = 12.58 MHz and fXX = 12.58 MHz
When Counting One Edge
When Counting Both Edges
Maximum frequency
fCLK/6 (2.10 MHz)
fCLK/6 (2.10 MHz)
Minimum pulse width
(High and low levels)
3/fCLK (0.24 µs)
3/fCLK (0.24 µs)
Maximum frequency
fXX/192 (65.52 kHz)
fXX/192 (65.52 kHz)
Minimum pulse width
(High and low levels)
96/fXX (7.63 µs)
96/fXX (7.63 µs)
Maximum frequency
fXX/384 (32.76 kHz)
fXX/384 (32.76 kHz)
Minimum pulse width
(High and low levels)
192/fXX (15.26 µs)
192/fXX (15.26 µs)
Maximum frequency
fXX/768 (16.38 kHz)
fXX/768 (16.38 kHz)
Minimum pulse width
(High and low levels)
384/fXX (30.52 µs)
384/fXX (30.52 µs)
Note Selected by means of the sampling clock selection register (SCS0)
10.2 Configuration
Timer/event counter 1 consists of the following registers:
• Timer counter (TM1/TM1W) × 1
• Compare register (CR10/CR10W) × 1
• Capture/Compare register (CR11/CR11W) × 1
• Capture register (CR12/CR12W) × 1
The block diagram of timer/event counter 1 is shown in Figure 10-1.
Preliminary User’s Manual U13987EJ1V0UM00
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