UPD784938 Datasheet, PDF (283/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 10 TIMER/EVENT COUNTER 1
10.4.2 Clear operation
(1) Clear operation after match with compare register and after capture operation
Timer counter 1 (TM1) can be cleared automatically after a match with the compare register (CR1n: n = 0, 1) and a capture
operation. When a clearance source arises, TM1 is cleared to 0H on the next count clock. Therefore, even if a clearance
source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives.
Figure 10-7. TM1 Clearance by Match with Compare Register (CR10, CR11)
Count clock
TM1
n-1
Compare register
(CR1n)
n
0
n
Count clock
TM1 and CR1n match Cleared here
Figure 10-8. TM1 Clearance after Capture Operation
TM1
n-1
n
0
1
1
2
INTP0
TM1 is captured
in CR11 here
Cleared here
(2) Clear operation by CE1 bit of timer control register 1 (TMC1)
Timer counter 1 (TM1) is also cleared when the CE1 bit of TMC1 is cleared (to 0) by software. The clear operation is
performed immediately after the clearance (to 0) of the CE1 bit.
Preliminary User’s Manual U13987EJ1V0UM00
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